The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down introduces challenges in maintaining process variations at acceptable levels within a wafer, wafer to wafer, and lot to lot. For example, as process geometries continue to decrease, critical dimension of features of a wafer are becoming continually smaller, and variations in the critical dimension across the wafer are increasing. As critical dimension variation increases, variation of performance characteristics of devices of the wafer also increase. For example, performance characteristics of transistors of a wafer, such as saturation drain current and threshold voltage, fluctuate with the critical dimension variation of transistor features of a wafer, such as gate widths, spacer widths, other features of the transistors, or combinations thereof. The fluctuating performance characteristics of the transistors can lead to poor device performance and low yield. Although existing methods and systems for compensating such performance characteristic variation have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.